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Mobile Multi-Output PWM Controller with Virtual Current SenseTM
POWER MANAGEMENT Description
The SC1404 is a multiple-output power supply controller designed to power battery operated systems. The SC1404 provides synchronous rectified buck converter control for two power supplies. An efficiency of 95% can be achieved. The SC1404 uses Semtech's proprietary Virtual Current SenseTM technology along with external error amplifier compensation to achieve enhanced stability and DC accuracy over a wide range of output filter components while maintaining fixed frequency operation. The SC1404 also provides two linear regulators for system housekeeping. The 5V linear regulator takes its input from the battery; for efficiency, the output is switched to the 5V output when available. The 12V linear regulator output is generated from a coupled inductor off the 5V switching regulator. Control functions include: power up sequencing, soft start, powergood signaling, and frequency synchronization. Line and load regulation is to +/-1% of the output voltage. The internal oscillator can be adjusted to 200 kHz or 300 kHz or synchronized to an external clock. The MOSFET drivers provide >1A peak drive current for fast MOSFET switching. The SC1404 includes a PSAVE# input to select pulse skipping mode for high efficiency at light load, or fixed frequency mode for low noise operation.
SC1404
Features
6 to 30V input range (operation possible below 6V) 3.3V and 5V dual synchronous outputs Fixed-frequency or PSAVE for maximum efficiency over wide load current range 5V/50mA linear regulator 12V/200mA linear regulator TM Virtual Current Sense for enhanced stability Accurate low-loss current limiting Out-of-phase switching reduces input capacitance External compensation supports wide range of output filter components for reduced cost Programmable power-up sequence Power Good output Output overvoltage & overcurrent protection with output undervoltage shutdown 4A typical shutdown current 6mW typical quiescent power
Applications
Notebook and Subnotebook Computers Automotive Electronics Desktop DC-DC Converters
Typical Application Circuit
I P U T + 6V to + 30V N + 5V A LW A Y S O N
0.1uF U4 22 0.22uF V+ 6 21 +
S C 1404 O N /O F F
10
4.7uF
SYNC
VL
+ 12V O U TP U T
12OUT VDD 4 5 + 4.7uF
S C 1404 O N /O F F
23 3 C7 25 0.1uF
SHDN COMP3
COMP5
12 C11 18 0.1uF + 2.2uF
BST3
SC1404
BST5
0.1uF
27 26
+ 3V O U TP U T
L1
DH3 PHASE3
DH5 PHASE5
16 17 0.1uF
T1
+ 5V O U TP U T
24 +
DL3
DL5 PGND
19 + 20 14 13 15 9 11 + 0.1uF
1 2
CSH3 CSL3
CSH5 CSL5 SEQ
+ 2.5V R E F
3V O N /O F F 5V O N /O F F
28 7
ON5
PSAVE
RUN/ON3 GND
REF RESET
PO W ER G O O D
Revision 4, July 2003
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SC1404
POWER MANAGEMENT Absolute Maximum Ratings
PAR AMETER VD D , V+, PHASE3, PHASE5 to GND PHASE3, PHASE5 to GND BST3, BST5, D H3, D H5 to GND PGND to GND VL to GND BST3 to PHASE3; D H3 to PHASE3; BST5 to PHASE5; D H5 to PHASE5 D ESC R IPTION Supply and Phase Voltages Phase Voltages Boost voltages Power Ground to Si gnal Ground Logi c Supply Hi gh-si de Gate D ri ve Supply Hi gh-si de Gate D ri ve Outputs Low-si de Gate D ri ve Outputs and C urrent Sense i nputs Logi c i nputs/outputs MAXIMU M -0.3 to +30 -2.0 (transi ent - 100 nsec) -0.3 to +36 0.3 -0.3 to +6 -0.3 to +6 -0.3 to (+BSTx + 0.3) -0.3 to +(VL + 0.3) -0.3 to +(VL + 0.3) -0.3 to +(V+ + 0.3V) C onti nuous +5 +50 -0.3 to (+VD D + 0.3) C onti nuous 12V output current Juncti on Temperature Range juncti on to ambi ent Storage Temperature Range Lead Temperature +200 +150 76 -65 to +200 +300 C , 10 second max. mA C C /Watt C C mA mA V
PRELIMINARY
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
U N ITS V V V V V V V V V V
D L3, D L5 to GND C SL5, C SH5, C SL3, C SH3 to GND REF, SYNC , SEQ, PSAVE#, ON5, RESET#, VL, FB3, FB5, C OMP3, C OMP5 to GND ON3, SHD N# to GND VL, REF Short to GND REF C urrent VL C urrent 12OUT to GND 12OUT Short to GND 12OUT C urrent TJ Package Thermal Resi stance TS TL
Electrical Characteristics
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
PAR AMETER
CODE
CONDITIONS MAIN SMPS CONTR OLLER S
MI N
T YP
MAX
UNITS
Inp ut Voltage Range 3V Outp ut Voltage 5V Outp ut Voltage Load Regulation Line Regulation
2003 Semtech Corp.
V IN V3OUT V5OUT V3LDRG V5LDRG V3LIRG V5LIRG V+ = 6.0 to 30V, 3V load = 0A to current limit V+ = 6.0 to 30V, 5V load = 0A to current limit Either SMPS, 0A to current limit, PSAVE# = VL Either SMPS, 6.0 < V+ < 30V, PSAVE# = VL
2
6 3.23 4.9 3.3 5.0 -0.4 0.05
30.0 3.37 5.1
V V V % % /V
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SC1404
POWER MANAGEMENT Electrical Characteristics Cont.
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
PAR AMETER Current-Limit Thresholds (N ote 2)
CODE I3LIMP I5LIMP I3LIMN I5LIMN ZC3 ZC5
CONDITIONS CSHX - CSLX (positive current) CSHX - CSLX (negative current) CSHX - CSLX PSAVE# = 0V, not tested From enable to 95% full current limit, with respect to fOSC
MI N 40
T YP 55 -50 5 512
MAX 70
UNITS mV
Zero Crossing Threshold Soft-Star t Ramp Time Oscillator Frequency Maximum Duty Factor SYN C Input High Pulse SYN C Input Low Pulse Width SYN C Rise/Fall Time SYN C Input Frequency Range Current-Sense Input Leakage Current
mV clks 380 230 kHz % ns
FOSCHI FOSCLO DF3MAX DF5MAX
SYN C = VL SYN C = 0V SYN C = VL SYN C = 0V N ot tested N ot tested N ot tested
220 170 92 94
300 200 94 96 300 300 200 240 350
SYN CRG ICSH3 ICSH5 CSH3 = 3.3V, CSH5 = 5.0V ER R OR AMP
kHz 10 A
3
DC Loop Gain Gain Bandwidth Product Output Resistance
DCG3, DCG5
From internal feedback node to COMP3/COMP5
18 8
V/V MHz Kohms
RC3, RC5
COMP3, COMP5 INTER NAL R EGULATOR AND R EFER ENCE
25
VL Output Voltage VL Undervoltage Lockout Fault Threshold VL Switchover Lockout REF Output Voltage REF Load Regulation
VLOUT V LU V VLSW REFOUT REFLD1 REFLD2
SHDN # = V+; 6V < V+ <30V, 0mA 4.6 3.5 3.7 4.5 2.45 2.5
5.25 4.1
V
2.55 12.5 50 mV
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SC1404
POWER MANAGEMENT Electrical Characteristics Cont.
PAR AMETER REF Sink Current REF Fault Lockout Voltage V+ Op erating Sup p ly Current V+ Standby Sup p ly Current V+ Shutdown Sup p ly Current Quiescent Power Consump tion CODE IREFSK REFUV IVPOP IVPSB IVPSD PQ CONDITIONS 10mV rise in REF voltage Falling edge VL switched over to VOUT5, 5V SMPS on, ILOAD5 = ILOAD3 = 0A, PSAVE# = 0V V+ = 6V to 30V, both SMPS off, PSAVE# = 0V; includes current into SHDN # V+ = 6V to 30V, SHDN # = 0V SMPS enabled, N o Load on SMPS FAULT DETECTION Overvoltage Trip Threshold Overvoltage-Fault Prop agation Delay Outp ut Undervoltage Threshold Outp ut Undervoltage Lockout Time Thermal Shutdown Threshold V3UV, V5UV V3OV, V5OV With resp ect to unloaded outp ut voltage Outp ut driven 2% above overvoltage trip V With resp ect to unloaded outp ut voltage 7 10 1.5 65 75 85 15 % s % -1 1.8 10 300 3 6 15 mW MI N T YP 10 2.2 50
PRELIMINARY
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
MAX
UNITS A V A
TH
V3UV TO V5UV TO
From each SMPS enabled, with resp ect to f
OSC
5000
6144
7000
clks
Typ ical hysteresis = 10C
+150
C
R ESET# RESET# Trip Threshold RESET# Prop agation Delay RESET# Delay T i me T3RSDL T5RSDL V3RST V5RST With resp ect to unloaded outp ut voltage, falling edge; typ ical hysteresis = 1% Falling edge, outp ut driven 2% below RESET# trip threshold With resp ect to fOSC INPUTS AND OUTPUTS Logic Inp ut Low Voltage Logic Inp ut High Voltage
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27,000
-12
-9 1.5
32,000
-5
% s
37,000
clks
VIO3, VIOP, VIO5, VIOSD, VIOSN VIH3, VIHP, VIH5, VIHSD, VIHSN
ON 3, PSAVE#, ON 5, SHDN #, SYN C (SEQ = REF) ON 3, PSAVE#, ON 5, SHDN #, SYN C (SEQ = REF)
4
0.6
V
2.4
V
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SC1404
POWER MANAGEMENT Electrical Characteristics Cont.
Unless otherwise noted: V+ = 15V, both PWMs on, SYNC = 0V, VL load = 0mA, REF load = 0mA, PSAVE# = 0V, TA =-40 to 85C. Typical values are at TA = +25C. Circuit = Typical Application Circuit
PAR AMETER Input Leakage Current PSAVE#, ON 5, SYN C Input Leakage Current - ON 3 Input Leakage Current SHDN # Logic Output Low Voltage Logic Output High Current ON 5 Pull-down Resistance Gate Driver Sink/Source Current Gate Driver On-Resistance
CODE ILP, IL5, ILSN IL 3 ILSD VORSTL IORSTH RON 5 IDL3, IDH3, IDL5, IDH5 RGBH3, RGHP3, RGBH5, RGHP5, RGVL3, RGLG3 RGVL5, RGLG5 ZN OV T
CONDITIONS SEQ = REF
MI N -1
T YP
MAX +1 +2
UNITS A A A V mA A
ON 3 = 15V SHDN # = 15V RESET#, ISIN K = 4mA RESET# = 3.5V ON 5, ON 3 = 0V, (SEQ = REF) DL3, DH3, DL5, DH5, forced to 2.5V BST3 to DH3, DH3 to PHASE3, BST5 to DH5, DH5 to PHASE5, VL to DL3, DL3 to PGN D, VL to DL5, DL5 to PGN D PHASE3, PHASE5 to GN D DHx falling edge to DLx rising edge DLx falling edge to DHx rising edge (1V threshold on DHx and DLx, no external capacitance on DL or DH) 12V LINEAR R EGULATOR
-2 -1 3
+10 0.4
1 100 1 1.5 7
N on-Overlap Threshold Shoot-through (N on-Overlap) Delay
1.0 10 35 17 75 25 115
V nsec nsec
VDD Shunt Threshold VDD Shunt Current VDD Leakage Current 12OUT Output Voltage 12OUT Current Limit 12OUT Regulation Threshold Quiescent VDD Current
VDDSHN IVDDST IVDDLK VOUT12 ILIM12 V12THR I12Q
Rising edge, hysteresis = 5% VDD = 20V VDD = 5V, Standby mode 0mA < Load < 200mA 12OUT forced to 11V, VDD = 13V Falling edge VDD = 18V, run mode, no 12OUT load
17 5 10
21 30 30
V mA A V mA
11.55 200
12.1
12.75
11.9 80 100
V A
Notes: (1) This device is ESD sensitive. Use of standard ESD handling procedures required. (2) Applicable from 0 to +85C.
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SC1404
POWER MANAGEMENT Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name CSH3 CSL3 COMP3 12OUT VDD SYN C ON 5 GN D REF PSAVE# RESET# COMP5 CSL5 CSH5 SEQ DH5 PHASE5 BST5 DL5 PGN D VL V+ SHDN # DL3 BST3 PHASE3 DH3 ON 3 Pin Functio n Current limit sense inp ut for 3V SMPS. Connect to the inductor side of a current sense resistor.
PRELIMINARY
Outp ut voltage sense inp ut for 3V SMPS. Connect to the outp ut side of a current sense resistor. The outp ut of the 3.3V SMPS error amp lifier. 12V internal linear regulator outp ut. Sup p ly voltage inp ut for the 12OUT linear regulator. Also connects internally to a 18V overvoltage shunt regulator clamp . Oscillator Synchronization and Frequency Select. Tie to VL for 300 kHz op eration; tie to GN D for 200 kHz. Drive externally to synchronize to an external oscillator between 240 kHz and 350 kHz. 5V ON /OFF Control Inp ut. Low noise Analog Ground and Feedback reference p oint. 2.5 V Reference Voltage outp ut. Byp ass to GN D with 1 F minimum. Logic inp ut that disables PSAVE Mode when high. Connect to GN D for normal use. Active-low timed Reset outp ut. RESET# swings from GN D to VL. RESET# goes high after a fixed 32,000 clock cycle delay following p ower up . The outp ut of the 5V SMPS error amp lifier. Outp ut voltage sense inp ut for 5V SMPS. Connect to the outp ut side of a current sense resistor. Current limit sense inp ut for 5V SMPS. Connect to the inductor side of a current sense resistor. Inp ut that selects SMPS p ower-up sequence and selects monitor voltage(s) used by RESET#. Gate Drive Outp ut for the 5V, high-side N -Channel switch. 5V switching node (inductor) connection. Boost cap acitor connection for 5V high-side gate drive. Gate drive outp ut for the 5V low-side synchronous rectifier MOSFET Power Ground. 5 V internal linear regulator outp ut. Battery Voltage inp ut. Shutdown control inp ut - active low. Gate drive outp ut for the 3V low-side synchronous rectifier MOSFET. Boost cap acitor connection for 3V high-side gate drive. 3V switching node (inductor) connection. Gate drive outp ut for the 3V high-side N -Channel switch. 3V ON /OFF Control Inp ut.
Note: All logic level inputs and outputs are open collector TTL compatible.
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SC1404
POWER MANAGEMENT Block Diagram
V+ V+ SYNC PSAVE VDD 12OUT + 4.7 f 200m A
VL 5V REG
12 V REG
VL VIN
+
2.2 f
VL
BST3 VIN DH3 LX3 +3.3V DL3 VL LS CSL5
EN DELAY HS
BST5
DH5 LX5 VL 1:3 T1 +5V
OSC
LS
DL5
PGND 50mV OC 3V CTL LOGIC 5V CTL LOGIC OC 50mV
7.5m V
PS
PS
7.5m V
2.5m V
PS POL
PS POL
2.5m V
CSH3 CSL3
PWM MODULATOR
OV FAULT
PWM MODULATOR
CSH5 CSL5
+10%
-25% COMP3 COMP5
UV FAULT
DELAY REF V+ CSL3 CSL5 CURRENT RAMP TIMER BV SS 3 TIME/ON5 VL 2 0.5 POW ER-ON SEQUENCE LOGIC 2.0 RESET
2.5V REF
SEQ
RUN/ON3
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SC1404
POWER MANAGEMENT Pin Configuration
Top View
C SH 3 C S L3 C OMP3 12OU T VD D SYN C ON 5 GN D R EF PSAVE# R E S E T# C OMP5 C S L5 C SH 5
PRELIMINARY Ordering Information
DEVICE
28 27 26 25 24 23 22 21 20 19 18 17 16 15
ON 3 DH3 PH ASE3 B S T3 D L3 SH D N # V+ VL PGN D D L5 B S T5 PH ASE5 DH5 SEQ
PACKAGE TSSOP-28 SSOP-28
TEMP. (TAMB) -40 - +85C
1 2 3 4 5 6 7 8 9 10 11 12 13 14
SC1404ITSTR SC1404ISSTR
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
TSSOP-28/SSOP-28
SC1404
Block Diagram
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SC1404
POWER MANAGEMENT Functional Information
Detailed Description The SC1404 is a versatile multiple-output power supply controller designed to power battery operated systems. Out-of-phase switching improves signal quality and reduces input RMS current, thereby reducing the size of input filter capacitors (see Out-ofPhase Switching). The SC1404 provides synchronous rectified buck control in fixed-frequency forced-continuous mode and in hysteretic PSAVE mode, for two switching converters over a wide load range. The two switchers have on-chip preset output voltages of 5.0V and 3.3V. The control and fault monitoring circuitry for each PWM controller includes digital softstart, turn-on sequencing, voltage error amplifier with built-in slope compensation, pulse width modulator, power save, over-current, over-voltage and undervoltage fault protection. Two linear regulators and a precision reference voltage are also provided. The 5V/50mA linear regulator (VL supply) which powers the SC1404 and gate drivers operates from the battery (V+ supply). If the 5V converter is running, the SC1404 disables the linear regulator and connects the VL supply to the 5V output through an internal switch. The operating current for the SC1404 and gate drivers then comes from the more efficient 5V converter. The 12V/200mA linear regulator can supply 200mA. Semtech's proprietary Virtual Current SenseTM provides advantages in stability and signal to noise ratio compared to conventional current sensing. PWM control There are two separate PWM control blocks for the 3V and 5V switchers. They are switched out-of-phase with each other. The interleaved topology offers advantages over in-phase solutions. It reduces steady state input filter requirements by reducing current drawn from the filter capacitors. To avoid both switchers switching simultaneously, there is a built-in time delay between the two switchers, the amount of which depends on the input voltage (see Out-of-Phase Switching). The PWM provides two modes of control over the entire load range: 1 - Forced continuous conduction mode as a fixed-frequency peak current mode controller with falling edge modulation, and 2 - Hysteretic Power-save mode. Current sense is done differently than that in the conventional peak current mode control. Semtech's proprietary Virtual Current SenseTM emulates the necessary inductor current information for proper functioning of the IC. When the switcher operates in continuous conduction mode, the high-side MOSFET turns on the beginning of each switching cycle. It is turned off when the desired duty cycle is reached. Active shootthrough protection will delay the low-side MOSFET turn-on until the phase node drops below 1.0 V. The low-side MOSFET then remains on until the beginning of the next switching cycle. Again, active shoot-through protection ensures that the gate to the lowside MOSFET has dropped low before the high-side MOSFET is turned on.
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Under light load conditions when the PSAVE pin is low, the SC1404 operates as a hysteretic controller in discontinuous conduction mode to reduce switching frequency and switching bias current. The switching frequency then is determined by the hysteretic trip voltage set around the reference. When entering PSAVE# mode, if the minimum (valley) inductor current as measured across the CSH and CSL pins is below the PSAVE# threshold for four switching cycles, the virtual current sense circuitry is shutdown and PWM control switches from forced continuous to hysteretic mode. If the minimum (valley) inductor current is above the threshold for four switching cycles, PWM control changes from hysteretic to forced continuous mode. The SC1404 provides built-in hysteresis to prevent chattering between the two modes of operation. Gate Drive / Control The SC1404 gate drivers are designed to switch large MOSFETs up to 350KHz. The high-side gate driver is required to drive the gate of high-side MOSFETs above the V+ input. The supply for the gate drivers is generated by charging a boostrap capacitor from the VL supply while the low-side driver is on. Monitoring circuitry ensures that the bootstrap capacitor is charged when coming out of shutdown or fault conditions where the bootstrap capacitor may be depleted. In continuous conduction mode, the low-side driver output that controls the low-side MOSFET is on when the high-side driver is off. Under light load conditions when the PSAVE# input is low, the inductor ripple current will approach the point where it reverses polarity. This is detected by the low-side driver control and the low-side MOSFET is turned off before the current goes significantly negative and causes energy drain from the output. The low-side driver operation is also affected by various fault conditions as described in the Fault Protection section. External Compensation The COMP pin allows external compensation of the feedback loop. This allows greater flexibility when choosing output filters, resulting in reduced cost and smaller size compared to a fixed compensation approach. A nominal gain of 18 for the error amplifier improves the system loop gain and output transient response. Internal Bias Supply The VL linear regulator provides a 5V output that powers the gate drivers, 2.5V reference, and internal controls of the SC1404. The VL supply can provide up to 50mA, but this must include MOSFET gate drive current. The VL pin should be bypassed to GND with 4.7uF to supply the peak gate drive curents. The VL regulator receives input power from the V+ battery input. Efficiency is improved by providing a boot-strap for the VL bias. When the 5V SMPS output voltage reaches 5V, internal circuitry detects this condition and turns on a PMOS pass device between CSL5 and VL. The internal VL regulator is then disabled and the VL bias is provided by the high efficiency 5V switcher.
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SC1404
POWER MANAGEMENT Functional Information
The REF output is accurate to +/- 2% over temperature. It is capable of delivering 5mA max and should be bypassed with 1uF minimum. Loading the REF pin will reduce the REF voltage slightly.
PRELIMINARY
SHDN # Low High ON 3 X Low ON 5 X Low MODE Shut-down Standby DESCRIPTION Minimum bias current VREF and VL regulator enable Both SMPS Ru n n i n g
Loading Resistance () Deviation from Vref = 2.4920V
511 8.3mV
2.67K 3.1mV
49.9K 0.5mV
255K 0.3mV
1Meg 0mV
High
High
High
Ru n Mode
Current Sense (CSH, CSL) The output current of the power supply is sensed as the voltage drop across an external resistor between the CSH and CSL pins. Overcurrent is detected when the current sense voltage exceeds +/- 50mV. A positive overcurrent will turn off the high-side driver, a negative overcurrent will turn off the low-side driver; each on a cycle-by-cycle basis. Oscillator When the SYNC pin is set high the oscillator runs at 300KHz; when SYNC is set low the frequency is 200KHz. The oscillator can also be synchronized to the falling edge of a clock on the SYNC pin with a frequency between 240KHz and 350KHz. In general, 200KHz operation is used for highest efficiency while 300KHz leads to less output ripple and/or smaller filter components. Fault Protection In addition to cycle-by-cycle current limit, the SC1404 monitors over-temperature, and output overvoltage and undervoltage conditions. The overtemperature detection will shut the part down if the die temperature exceeds 150C with 10C of hysteresis. If either SMPS output is more than 10% above its nominal value, both SMPS are latched off and the low-side MOSFETS are latched on. To prevent the output from ringing too far below ground in a fault condition, a 1A Schottky diode should be placed across each output. Two different levels of undervoltage are detected. If the output falls 10% below its nominal output, the RESET# output is pulled low.If the output falls 25% below its nominal output following a start-up delay, both SMPS are latched off. Both of the latched fault modes persist until SHDN# or ON3 is toggled, or the V+ input is brought below 1V. Shutdown and Operating Modes Holding the SHDN# pin low disables the SC1404, reducing the V+ input current to less than 10uA. When SHDN goes high, the part enters a standby mode where the VL regulator and VREF are enabled. Turning on either SMPS will put the SC1404 in run mode.
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Power up Controls and Soft Start The user has control of the SC1404 RESET# by setting the SEQ, ON3 and ON5 pins as described in the following table. At startup, the RESET# pin is held low for 32K switching cycles. Another timer is used to enable the undervoltage protection. The undervoltage protection circuitry is enabled after 6144 switching cycles, at which time the SMPS should be in regulation. When SEQ is set to REF, the RESET# only monitors the 3.3V SMPS and the 5V SMPS is ignored. Each SMPS contains its own counter and DAC to gradually increase the current limit at startup to prevent surge currents. The current limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly over the course of 512 switching cycles. 12OUT Supply The 12OUT linear regulator is capable of supplying 200mA. The input voltage to the 12OUT regulator is generated by a secondary winding on the 5V SMPS inductor. A heavy load on the 12OUT regulator when the 5V SMPS is in PSAVE will cause the VDD input to drop, browning out the regulator. If the output drops 0.8% from its nominal value, the 5V SMPS is forced out of PSAVE mode and into continuous conduction mode for several cycles. This recharges the bulk input capacitor on the VDD. The 12OUT linear regulator also has a current limit to prevent damage under short circuit conditions. Over-voltage protection is provided on the VDD input. If the VDD input is above 19V, an over-voltage is detected and a 10mA current shunt load is applied to VDD. The over-voltage threshold has a 0.5V hysteresis.
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SC1404
POWER MANAGEMENT Functional Information SC1404 Startup Sequence Chart
SEQ REF REF REF REF GN D GN D VL VL ON 3 LOW LOW HIGH HIGH LOW HIGH LOW HIGH ON 5 LOW HIGH LOW HIGH X HIGH/LOW X HIGH/LOW RESET# Follows 3.3V SMPS. Low. Follows 3.3V SMPS. Follows 3.3V SMPS. Low. High after both outputs are in regulation. Low. High after both outputs are in regulation. DESCRIPTION Independant star t control mode. Both SMPSs off. 5V SMPS ON , 3.3V SMPS OFF. 3.3V SMPS ON , 5V SMPS OFF. Both SMPSs on. Both SMPSs off. 5V star ts when ON 3 goes high. If ON 5= HIGH, 3V is on. IF ON 5 = LOW, 3V is off. Both SMPSs off. 3V star ts when ON 3 goes high. If ON 5 = HIGH, 5V is on. IF ON 5 = LOW, 5V is off.
Applications Information
Reference Circuit Design Introduction The SC1404 is a versatile dual switching regulator with fixed 5V and 3.3V outputs . In addition, there is an on-chip 5V linear regulator capable of supplying 50mA output current and a 12V linear regulator able to provide 200mA. The SC1404 is designed for notebook applications but has is suited to applications where high efficiency, small package, and low cost are required. Design Guidelines The schematic for the reference circuit is shown on page 22. The reference circuit is configured as follows: Switching Regulator 1 Switching Regulator 2 Linear Regulator 1 Linear Regulator 2 Designing the Output Filter Before calculating the output filter inductance and output capacitance, an acceptable amount of output ripple current must be determined. The maximum allowable ripple current depends on the transient requirement of the power supply. Under normal situation, the ripple current is usually set around 10 to 20% of the Vout1 = 3.3V @ 6A Vout2 = 5.0V @ 6A Vout3 = 12V, 200mA Vout3 = 5.0V @ 50mA
maximum load. However, in order to speed up the output transient response, ripple current can be much higher. In this design, we are going to set the ripple current to be 40% of maximum load. So once the ripple voltage specification is determined, the capacitor ESR is chosen. The output ripple voltage is usually specified at +/ - 1% of the output voltage. For the reference circuit 3.3V switcher, we selected a maximum ripple voltage of 33mV. Choosing one 180uF, 4V Panasonic SP Polymer Aluminum Electrolytic Cap, of which ESR is 15 m , sets the maximum ripple current as follows:
IO = VO _ MAX ESR IO = 0.033 V = 2.2A 0.015
Checking to see if the maximum RMS current can be met by the SP cap.
IRMS =
I1 2 + I1 I2 + I2 2 3
I1 = -
IO 2
I2 = +
IO 2
Irms=0.635 A << Irms_rated=3.0A The output inductance can now be found by:
LO =
( VIN _ NOM - VO) DNOM TS IO
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SC1404
POWER MANAGEMENT Applications Information
where Vin_nom=15V, Vo=3.3V, D=Vo/Vin_nom, Fs=300KHz, Ts=3.33uS and Io=2.2 A. Lo is then calculated to be 3.9uH. For the interest of this design, Lo is chosen to be 4.7uH for the 3.3V output. For the 5V output, a coupled inductor with 6.4uH primary (5V winding) inductance is used. Choosing Current Sense Resistor Since the SC1404 implements Virtual Current SenseTM, an external current sense resistor is not needed by the control loop. But it is required for cycle-by-cycle current limit. Cycle-by-cycle current limit is reached when the voltage across the current sense resistor exceeds 50mV nominal. Depending on the system requirement, this current limit can vary, it is usually 10 to 30% higher than the maximum load. Taking into consideration lower limit of the 50mV, the value of the current sense resistor can be calculated using the following equation:
40mV (min) RSENSE = IPK _ OC
Vendor P/N Si4886DY IRF7413 FDS9412 STS12N F30L VDS (V) 30 30 30 30 ID ( A ) 13 13 7.9 12
PRELIMINARY
Rds(0n) @ 4.5V (ohm) 0.0135 0.011 0.036 0.0085 Package so-8 so-8 so-8 so-8
The following calculations are done to verify that the power dissipation of the main switch MOSFET is well within 1.86W, which is the maximum allowable power dissipation for the package.
PTOTAL _ DISS = PCONDUCTION + PSWITCHING + PGATE PCONDUCTION = Rds ( on) IRMS 2 Dnom
For a DC OC trip point between 8 to 12A, Rsense is chosen to be 5m . Choosing the Main Switching MOSFET Before choosing the main switch MOSFET, we need to know two critical parameters: voltage and current rating. In order to minimize the conduction loss, we recommend using the lowest Rds(on) for the same voltage and current rating. The maximum drain to source voltage of the switch MOSFET is mainly decided by the topology of the switcher. Since this is a buck topology, VDS _ MAX = VIN _ MAX = 21 V Applying a derating of 70%, a 30V MOSFET is used in the design. The peak current of the MOSFET is determined by
where Rds(on) = 0.01 @Tj=25 C and Vgs = 4.5V. In order to find Rds(on)@ Tj=100 C , use 1.40*Rds(on)@25 C . Therefore, Rds(on) @ Tj = 100 C is equal to 0.014 .
IRMS = (
where
I1 2 + I1 I2 + I2 2 ) Dnom 3
IO _ MAX IO _ MAX I1 = IMAX + = 7.1A, I2 = IMAX - = 4.9A and 2 2
Dnom = VOUT VIN _ NOM
The worst case conduction loss is calculated to be 25mW. And the switching loss of the MOSFET is given by,
PSWITCHING = CRSS VIN 2 fS IOUT IG
60mV = 11 A 5.5m According to the calculated voltage and current rating, Si4886DY, IRF7413, FDS9412 or STS12NF30L meets the requirement. The specs for these MOSFETs are listed in the table below. For the purpose of this exercise, STS12NF30L is chosen. Next step is to determine its power handling capability. Based on 85 C ambient temperature, 150 C junction temperature and 50 C /W thermal resistance, its power handling is calculated as follows: IPEAK =
TJ = 150C; TA = 85C; JA= 50C/W
where Crss is the reverse transfer capacitance of the MOSFET; it is equal to 200pF for STS12NF30L, Ig is the gate driver current; it is equal to 1A for SC1404. And Vin_nom = 15V, fs = 300KHz. The switching loss is calculated to 81mW. And the gate loss is given by,
PGATE =
1 CG V 2 fS 2
where Cg=11nF, V=5V and fs=300KHz. The gate loss is calculated to be 41mW. So the total power dissipation is calculated to be 147mW and is well within the maximum power dissipation allowance of the MOSFET. No special heating sinking is required when laying out the MOSFET.
PT =
TJ - TA 150 - 85 = = 1.30W JA 50
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SC1404
POWER MANAGEMENT Applications Information Applications Information
Designing the Loop There are two aspects concerning the loop design. One is the power train design and the other is the external compensation design. A good loop design is a combination of the two. In the SC1404, the control-to-output/power train response is dominated by the load impedance, the effective current sense resistor, output capacitance, and the ESR of the output caps. The low frequency gain is dominated by the output load impedance and the effective current sense resistor. Inherent to Virtual Current SenseTM, there is one additional low frequency pole sitting between 100Hz and 1KHz and a zero between 15KHz and 25KHz. To compensate for the SC1404 is easy since the output of error amplifier COMP pin is available for external compensation. A traditional pole-zeropole compensation is not necessary in the design using SC1404. To ensure high phase margin at crossover frequency while minimizing the component count, a simple high frequency pole is often sufficient. In the reference design below, single-pole compensation method is demonstrated. And the loop measurement results are compared to that obtained from the simulation model. Transient response is also done to validate the model. Also, to help speeding up the design process, a list of recommended output caps vs. compensation caps value is given in table I. Single-Pole compensation Method Given parameters: Vin = 19V, Vout = 3.3V @ 2.2A, Output impedance, Ro = 3.3V/2.2A = 1.5 , Panasonic SP cap, Co = 180uF, Resr = 15 m , Output inductor, Lo = 4.7uH Switching frequency, Fs = 300KHz Simulated Control-to-Output gain & phase response (up to 100KHz) is plotted below
Phase (deg)
200 150 100 50 Phase (deg) 0 -50 -100 -150 -200 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
Measured Control-to-Output gain & phase response (up to 100KHz) is plotted below.
50 40 30 20
Gain (dB)
10 0 -10 -20 -30 -40 -50 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
200 150 100 50 0 -50 -100 -150
.
50 40 30 20 10 Gain (dB) 0 -10 -20 -30 -40 -50 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
-200 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
Single-pole compensation of the error amplifier is achieved by connecting a 100pF capacitor from the COMP pin of the SC1404 to ground. The simulated feedback gain & phase response (up to 100KHz) is plotted below.
.
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SC1404
POWER MANAGEMENT Applications Information
25 20
-20 20 0
PRELIMINARY
15
Phase (deg)
-40 -60 -80 -100 -120 -140 -160 -180
10 Gain (dB) 5 0 -5 -10 -15 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
1.00E+02
1.00E+03 Frequency (Hz)
1.00E+04
1.00E+05
0 -10 -20
Simulated overall gain & phase responses (up to 100KHz) is plotted below.
80 60
-30 Phase (deg) -40 -50 -60 -70 -80 -90 -100 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
-80 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05 -40 -60 Gain (dB) 40 20 0 -20
Measured feedback gain & phase responses (up to 100KHz) is plotted below.
25 20 15 10 Gain (dB) 5 0 -5 -10 -15 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
180 160 140 120 Phase (deg) 100 80 60 40 20 0 -20 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
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SC1404
POWER MANAGEMENT Applications Information
Measured overall gain & phase response of the single-pole compensation using SC1404 is plotted below.
60
Table I. is useful only if the following ESR condition is satisfied.
fO = 1 2 RESR CO
25
fo > 50KHz where Resr is the equivalent ESR of the total output caps. For instance, if two Panasonic SP cap 180uF, 15 m are used. The equivalent Resr = ESR(single)/2 = 7.5 m . The error amplifier compensation is set by the internal output resistance of the amplifier (25 Kohms typical) and the external impedance attached to the COMP pin. Connecting a single capacitor to the COMP pin places a R-C pole into the error amplifier.
1.00E+03 f (Hz) 1.00E+04 1.00E+05
Gain (dB)
Phase (deg)
-10
-45
-80 1.00E+02
180 160 140 120 100 80 60 40 20 0 -20 1.00E+02 1.00E+03 f (Hz) 1.00E+04 1.00E+05
Table I. Recommended compensation cap for different output capacitance.
Output Cap
Recommended Compensation Cap Value 100pF
<= 180uF >180uF & < 1000uF >1000uF
200pF 330pF
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SC1404
POWER MANAGEMENT Applications Information
Input Capacitor Selection/Out-of-phase Switching The SC1404 uses out-of-phase switching between the two converters to reduce input ripple current, enabling the use of smaller, cheaper input capacitors when compared to in-phase switching. The two approaches are shown in the following figures. The first figure shows in-phase switching: I3in is the input current drawn by the 3.3V converter, I5in is the input current drawn by the 5V converter. The two converters start each switching cycle simultaneously, resulting in a significant amount of overlap. This overlap increases the peak current. The total input current to the converter is the third trace Iin, which shows how the two currents add together. The fourth trace shows the current flowing in and out of the input capacitors. In-phase Switching
I3in
PRELIMINARY
As the input voltage is reduced, the duty cycle of both converters increases, as shown in the following figure. For inputs less than 8.3 volts it is impossible to prevent overlap when producing 3.3V and 5V outputs, regardless of the phase relationship between the converters.
period phase lead
I3in
I5in Iin average
0
0
I5in
Icap
Iin
average 0
0 Icap
From an input filter standpoint it is desirable to minimize the overlap, but it is also desirable to keep the turn-on and turn-off transitions of the two converters separated in time, otherwise the two converters may affect each other due to switching noise. The SC1404 implements this by changing the phase relationship between the converter depending on the input voltage.
Inp ut voltage Vin > 9.6 V 9.6V > Vin > 6.7V 6.7 > Vin Phase lead from 3V conver ter rising edge to 5V conver ter rising edge 41% of switching p eriod 59% of switching p eriod 64% of switching p eriod
The next figure shows out-of-phase switching. Since the 3.3V and 5V converters are spaced apart, there is no resulting overlap. This results in a two benefits; the peak current is reduced and the frequency content is higher, both of which make filtering easier. The third trace shows the total input current, and the fourth trace shows the current in and out of the input capacitors. The RMS value of this current is significantly lower than the in-phase case and allows for smaller capacitors due to reduced RMS current ratings. Out-of-phase Switching
I3in
Vin > 9.6V: 3.3V turn-on leads 5V turn-on by 41% of the switching period. With Vin > 9.6V it is always possible to achieve no overlap, which minimizes the input ripple current. At Vin = 9.6V there is no overlap, but the 3.3V turn-on is nearing the 5V turn-off. 6.7 < Vin < 9.6V: 3.3V turn-on leads 5V turn-on by 59% of the period. To prevent the 3V turn-on from coinciding with the 5V turn-off (which could adversely affect either output), the 5V pulse is delayed in time slightly such that the 3V turn-on occurs before the 5V turn-off. This creates a small overlap between the 3V turn-on and the 5V turn-off, with a resulting slight increase in RMS input ripple, but this is preferred since it greatly reduces noise problems caused by simultaneous transitions. Note that at Vin = 6.7, the 3V turn-off is nearing the 5V turn-on.
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I5in
average Iin 0
Icap
0
2003 Semtech Corp.
SC1404
POWER MANAGEMENT Typical Characteristics
Vin < 6.7 volts: 3.3V turn-on leads 5V turn-on by 64% of the period. The 5V turn-on is delayed slightly more to add separation between the 3V turn-off and 5V turn-on. This leads to more overlap, but at this point overlap is unavoidable. Input ripple current calculations: The following equations provide quick approximations for input ripple current: D3 = 3.3V duty cycle = 3.3/Vin D5 = 5V duty cycle = 5/Vin I3 = 3.3V load current I5 = 5V load current Dovl = overlapping duty cycle of the 3V and 5V pulses, which varies according to input voltage: Vin > 9.6V: Dovl = 0 9.6V > Vin > 6.7V: Dovl = D5 - 0.41 6.7V > Vin Dovl = D5 - 0.36 Iin = D3 . I3 + D5 . I5 (average current drawn from Vin) Isw_rms = rms current flowing into 3V and 5V SMPS (Isw_rms)2 = Dovl . (I3 + I5)2 + (D3 - Dovl) . I32 + (D5 -Dovl) . I52 Irms_cap =
Isw_rms + Iin
2 2
IF _ AVG = ILOAD
100n = 0.2A TS
where 100nsec is the estimated time between the MOSFET turning off and the Schottky diode taking over and Ts = 3.33uS. Therefore a Schottky diode with a forward current of 0.5A is sufficient for this design. Operation below 6V input The SC1404 will operate below 6V input voltage with careful design, but there are limitations. The first limitation is the maximum available duty cycle from the SC1404, which limits the obtainable output voltage. The design should minimize all circuit losses through the system in order to deliver maximum power to the output. A second limitation with operation below 6V is transient response. When load current increases rapidly, the output voltage drops slightly; the feedback loop normally increases duty cycle briefly to bring the output voltage back up. If duty cycle is already near the maximum limit, the duty cycle cannot increase enough to meet the demand, and the output voltage sags more than normal. This problem can not be solved by changing the feedback compensation, it is a function of the input voltage, duty cycle, and inductor and capacitor values. If an application requires 5V output from an input voltage below 6V, the following guidelines should be used: 1 - Set the switching frequency to 200 kHz (Tie SYNC to GND). This increases the maximum duty cycle compared to 300 kHz operation. 2 - Minimize the resistance in the power train. Select MOSFETs, inductor, and current sense resistor to provide the lowest resistance as is practical. 3 - Minimize the pcb resistance for all traces carrying high current. This includes traces to the input capacitors, MOSFETS and diodes, inductor, current sense resistor, and output capacitor. 4 - Minimize the resistance between the SC1404 circuit and the power source (battery, battery charger, AC adaptor). 5 - Use low ESR capacitors on the input to prevent the input voltage dropping during on-time. 6 - If large load transients are expected, high capacitance and low ESR capacitors should be used on both the input and output.
The worst-case ripple current varies by application. For the case of I3 = I5 = 6A, the worst-case ripple occurs at Vin = 7.5V, at which point the rms capacitor ripple current is 4.2 amps. To handle this the reference design uses 4 paralleled ceramic capacitors, (Murata GRM32NF51E106Z, 10 uF 25V, size 1210). Each capacitor is rated at 2.2 Amps, allowing for derating at higher temperatures. Choosing Synchronous MOSFET and Schottky diode Since this is a buck topology, the voltage and current ratings of the synchronous MOSFET are similar to the high-side MOSFET. It makes sense cost-volume-wise to use the same MOSFET for both the main switch and synchronous MOSFET. Therefore, STS12NF30L is used again in the design for synchronous MOSFET. To improve overall efficiency, an external schottky diode is used in parallel to the synchronous MOSFET. The freewheeling current goes into the schottky diode instead of the body diode of the synchronous MOSFET, which usually has very high forward drop and slow transient behavior. It is important when laying out the board to place both the synchronous MOSFET and Schottky diode close to each other to reduce the current ramp-up and ramp-down time due to parasitic inductance between the channel of the MOSFET and the Schottky diode. The current rating of the Schottky diode can be determined by the following equation.
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SC1404
POWER MANAGEMENT
5V Start-up with slow Vin ramp. Proper startup of the 5V output can be hampered by slow dV/dt on the input. The SC1404 will power up and attempt to generate an output when the input voltage exceeds 4.5 volts. If the input has a slow dV/dt, the input voltage will not rise significantly during the start-up sequence, leading to two conditions. First, the VL supply can be hundreds of mV below 5V, since the input may not yet be above 5V. Second, the duty cycle will be at maximum, leading to very small off-times. These two conditions tend to reduce the BOOST voltage; if continued indefinitely, the BOOST capacitor may be unable to recharge fully, and eventually the high-side driver loses its BOOST bias. To avoid this the following steps should be taken: The following guidelines for 12V loading apply to the typical circuit, page 22.
PRELIMINARY
Vin range >10V 7V - 10V
12V load conditions 12V load < 1/2 * 5V load 12V load = 200mA max 12V load < 1/2 * 5V load Linearly derate 12V load: 200mA at 10V 100mA at 7V 12V load < 1/2 * 5V load Linearly derate 12V load: 100mA at 10V 25mA at 7V
6V - 7V
1. If possible the dV/dt of the input supply should exceed .02V/ usec. This dV/dt condition only applies when the input passes between 4 and 6 volts, the point at which the SC1404 begins a startup sequence. An alternative is to make sure the input voltage reaches 6 volts within 100 usec of SC1404 startup at approximately 4.2 volts. This is sufficiently fast to allow VL and duty cycle to achieve normal levels and will prevents the BOOST voltage from falling. 2. If the dV/dt of the input cannot meet condition 1, the startup of the SC1404 should be delayed until the input voltage reaches 6V. This can be done using either the SHDN# or ON5 pin. If the dV/dt is moderate (slews from 4 to 6 volts in several msecs), an RC delay on either the SHDN# or ON5 pin should be enough to delay turn-on until the input reaches 6V. 3. For slow dV/dt on the input (10's of msec), the SC1404 should be held off until the input reaches 6V. This can be done using a comparator or external logic to hold the SHDN# or ON5 pin low until the input reaches 6V. 12V Load Limitations The 12V regulator derives input power from a secondary winding on the 5V inductor. During the 5V off-time, the inductor transfers energy from the 5V winding to the secondary winding, thereby providing a crudely regulated 15V that feeds the 12V regulator. Note that duty cycle increases at low input voltages, and therefore the on-time decreases. At low input voltages, the duty cycle increases to maintain the 5V output. The off-time consequently decreases, which has two detrimental effects. It allows less time to recharge the raw 15V capacitor, and it also raises the peak 15V current required to maintain the average 12V load. The 15V winding needs higher peak current, delivered in less time. But the stray (leakage) inductance of the inductor resists rapid changes in winding current, and ultimately limits how much current can be drawn from 15V before the voltage falls.
PSAVE operation The SC1404 enters power-save operation if the load is sufficiently light, and if PSAVE is tied low. In PSAVE operation, the switching frequency is no longer fixed, and the converter operates as a hysteretic converter. This reduces gate drive losses and other switching losses to improve efficiency. Each converter willl enter or exit PSAVE operation independently, based on load current. The hysteresis (output ripple) on the 5V output is typically 70mV, and the 3V hysteresis is typically 35mV.
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SC1404
POWER MANAGEMENT
Overvoltage Test Measuring the overvoltage trip point can be problematic. Any buck converter with synchronous MOSFETS can act as a boost converter, sending energy from output to input. In some cases the energy sent to the input is enough to drive the input voltage beyond normal levels, causing input overvoltage. To prevent this, enable the SC1404 PSAVE# feature, which effectively disables the low side MOSFET drive so that little energy, if any, is transferred back to the input. Semtech recommends the following circuit for measuring the overvoltage trip point. D1 prevents the output voltage from damaging lab supply 1. R1 limits the amount of energy that can be cycled from the output to the input. R2 absorbs the energy that might flow from output to input, and D2 protects lab supply from possible damage. The ON5 signal is monitored to indicate when overvoltage occurs. Initial conditions: Both lab supplies set to zero volts No load connected to 3V or 5V PSAVE# enabled (PSAVE# tied to GND) ON5 enabled ON3 enabled DVMs monitoring ON5 and the output under test. Oscilloscope probe connected to Phase Node of the output under test (not strictly required). Set Lab Supply 2 to provide 10V at the SC1404 input. The phase node of the output being tested should show some switching activity. The ON5 pin should be above 4V. Slowly increase Lab Supply 1 until the output under test rises slightly above it's normal DC level. As Lab Supply 1 increases, switching activity at the phase node will cease. The ON5 pin should remain above 4V. Increase Lab Supply 1 in very small increments, monitoring both ON5 and the output under test. The overvoltage trip point is the highest voltage seen at the output before ON5 pulls low (approximately 0.3V). Do not record the voltage seen at the output after ON5 has pulled low; when ON5 pulls low, the current flowing in D1 changes, corrupting the voltage seen at the output.
to DVM D1 e.g. 1N4004 R1 75 1/2W 1K Lab Supply 1
D1 e.g. 1N4004
Vin
Output under test VL
Lab Supply 2
R2 470 1/2W
SC1404 Evaluation Board
ON5
to DVM
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SC1404
POWER MANAGEMENT Layout Guidelines
As with any high frequency switching regulator design, a good PCB layout is very essential in order to achieve optimum noise, efficiency, and stability performance of the converter. Before starting to layout the PCB, a careful layout strategy is strongly recommended. See the PCB layout in the SC1404 Evaluation Kit manual for example. In most applications, we recommend to use FR4 with 4 or more layers and at least 2 oz copper (for output current up to 6A). Use at least one inner layer for ground connection. And it is always a good practice to tie signal ground and power ground at one single point so that the signal ground is not easily contaminated. Also be sure that high current paths have low inductance and resistance by making trace widths as wide as possible and lengths as short as possible. Properly decouple lines that pull large amounts of current in short periods of time. The following step by step layout strategy should be used in order to fully utilize the potential of SC1404. Step #1. Power train components placement. a. Power train arrangement. Place power train components first. The figure below shows the recommended power train arrangement. Q1 is the main switching FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode and L1 is the output inductor. The phase node, where the source c. Gate Drive. SC1404 has built-in gate drivers capable of sinking/sourcing 1A peaks. Upper gate drive signals are noisier than the lower ones. Therefore, place them away from sensitive analog circuitries. Make sure the lower gate traces are as close as possible to the IC pins and both upper and lower gate traces as wide as possible. Step #2: PWM controller placement (pins) and signal ground island. Connect all analog grounds to a separate solid copper island plane, which connects to the SC1404's GND pin. This includes REF, COMP3, COMP5, SYNC, RUN/ON3, ON5, PSV# and RESET#. of the upper switching FET and the drain of the synchronous rectifier meets, since it switches at very high rate of speed, is generally the largest source of common-mode noise in the converter circuit. It should be kept to a minimum size consistent with its connectivity and current carrying requirements. Also place the Schottky diode as close to the phase node as possible to minimize the trace inductance, to reduce the efficiency loss due to the current rampup and down time. This becomes extremely important when the converter needs to handle high di/dt requirements. Step #3: Ground plane arrangement. There are several ways to tie the different grounds together. Since this is a buck topology converter, the output ground is relatively quieter than the input ground. Therefore connect analog ground to power ground at the output side. Often it is useful to use a separate ground symbol for the two grounds, and tie the two grounds together at a single point through a 0 resistor. The power ground for the input side and the power ground for the output side is the same ground and they can be tied together using internal planes.
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PRELIMINARY
b. Current Sense. Minimize the length of current sense signal trace. Keep it less than 15mm. Kelvin connections should be used; try to keep the traces parallel to each other and route them close to each other as much as possible. Even though SC1404 implements Virtual Current Sense scheme, the current sense signal is sampled by the SC1404 to determine the PSAVE threshold. See the following figure for a Kelvin connection of the current sense signal.
L1
SC1404
CSH CSL
Rcs
Q1 D1 Q2 L1
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SC1404
POWER MANAGEMENT Typical Characteristics
3.3V Efficiency
100 Efficiency (%) 90 80 70 60 50 0.01 0.1 1 10 Load Current (A) 6V 10V 19V
5V Efficiency
100 Efficiency (%) 95 90 85 80 0.01 0.1
6V
10V
19V
1
10
Load Current (A)
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NEG
J24 R1 2 10 2 1 BAT54A JP4 1 VL 8 7 6 5 C13 100pF C14 100pF V+ J27 V+ D1 1 1 COMP3 COMP5
C3 0.22uF 1 C4 0.22uF 2 2
2
1
1
1
GND
GND
GND
1
5 6 7 8
7
1 3 2 1 1 C15 1 2 3 2 LX3 2 DL3 T/L2 TTI8215 8 7 6 5 DL5
D
J6
2 5 6 7 8 LX5 0 0.22uF 1 10 6 5 0.22uF R5 C16
B_JACK_PAIR
LX3
R4 0 1
BST5 J23 LX5
POS
D
1
3_3V
R6 R7
0.005
1
L1
4
3_3V
J22 4 DH3 1
NEG
2
IRF7413
BST3R
BST5R
30BQ015 A C
C
C
C
23
22
28
26
21
20
25
24
27
19
18
17
16
15
D3 140T3 4 SEQ A R22 0 Ohm V+ VL 1 2 3 DL3 DL5 DH3 DH5 BST3 SHDN PGND R19 NO_POP A BST5 SEQ PHASE3 PHASE5
RUN/ON3
3 2 1
C39 1uF
R23 0 ohm
D5 140T3
J19 1 VL CSH5 2
A
NO_POP
C20
D4
30BQ015 J20 R21 NO_POP 1 CSL5
U1
2 JP1 1 1 CSL5 CSH5 1 JP2 2 JP3 CSL3 COMP3 12OUT VDD SYNC TIME/ON5 GND REF PSAVE RESET COMP5
J17 1 2 3 4 5 6 7 8 12 13 10 11 14 1 9 CSH3 CSH3 COMP3 RESET# REF SY NC ON3 1 2 R13 2M 1 1 1 R16 1k R17 5 4 3 2 1 S1 DIP_SW5_PTH VIN 6 7 8 9 10 VL C27 0.01uF VIN 2 T-ON5 2M 1 2 R15 2M 2 SHDN# 1 R14 2M 2 R12 2M 2 VDD PSV# C25 1uF/16V C26 0.1uF COMP5 CSH5
J21
1
CSL3
C29 NO_POP
C35 0.1uF
C36 0.1uF
CSH3
22
SC1404ITS
C34 0.1uF C43 NO_POP C37 0.01uF
C38 1uF
R18 NO_POP
C28 NO_POP
C33 0.1uF
+12V
J25
1
+12V
2
1 1
NEG
2003 Semtech Corp.
VDD
VIN
B_JACK_PAIR
J1 C5 10uF/25V C6 10uF/25V
POS
1
VIN
2
2
1
VIN
C1 10uF/25V 1
1
C2 10uF/25V
J2
J3
J4
J5
GND
C9
4.7uF/35V 4.7uF/16V C10 0.1uF
POWER MANAGEMENT Evaluation Board Schematic
C11
D
C12 0.1uF
Q1 IRF7413
DH5 4
D6 MBRS1100T3
Q2 IRF7413
BST3 4.7uF/25V C41 NO_POP
D
J16
C42
3_3V
1
0.005
6.8uH
J18
1 5V
5V
J7 B_JACK_PAIR 5V
180uF/4V Q3 4 NO_POP
C17 IRF7413 Q4
R20
D2
NO_POP
C18
150uF/6.3V
1
POS
C19
RESET# J12 RESET# J8 REF REF J10
1
GND
J26
C22
1
4.7uF/16V
C40 0.1uF
PSV#
SYNC
J9
1
ON3
1
J11
T-ON5
1
J13
1
VL VL J14
SHDN#
1
J15
SC1404 EVB Schematic
PRELIMINARY
SC1404
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SC1404
POWER MANAGEMENT Evaluation Board Bill of Materials
ITEM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 2 1 QT Y 4 1 DESIGNATION C1,C2,C5,C6 C3, C4, C15, C16 C9 C10,C12,C26,C33,C34,C35,C36,C40 C11,C22 C14,C13 C17 C19 C25 C37,C27 C39,C38 C42 D1 D2, D4 D3, D5 D6 BAT54A 30BQ015 MBRS140T3 MBRS1100T3 40V, 1A Schottky Y475M250N ECJ1VC1H101K EEF-UE0G181R EEF-UE0J151R ECJ3FB1C105 ECJ1VB1C104K PAR T NUMBER GRM230Y5V106Z025 DESCR IPTION 10uF, 25V 0.22uF, 50V, Y5V 4.7uF, 35V 0.1uF,50V, X7R 4.7uF, 16V 100pF, 50V 180uF, 4V 150uF, 6.3V 1uF, 16V 0.01uF, 50V 1uF 4.7uF, 25V 30V, 200ma, dual C_Anode Zetex I. R . Motorola Motorola SOT-23 SMC SMB SMB Panasonic N ovacap Panasonic Panasonic Panasonic Panasonic Panasonic MANUFACTUR ER Murata Panasonic FOR M FACTOR 1210 805 B_case 0603 1812 0603 D_Case_7343 D_Case_7343 1206 0603 0603
2003 Semtech Corp.
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SC1404
POWER MANAGEMENT Evaluation Board Bill of Materials Cont.
ITEM 17 18 19 20 21 22 23 24 25 26 27 28 29 QT Y 4 3 24 1 4 1 4 2 5 1 1 DESIGNATION JP1, JP2, JP3, JP4 J1, J6, J7 J2-J5, J8-J27 L1 Q1, Q2, Q3, Q4 R1 R4, R5, R22, R23 R6, R7 R12, R13, R14, R15, R17 R16 SW1 T/L2 U1 TTI-8215 SC1404ITS DR127-6R8 IRF7413 Any Any WSL2512R005FB43 Any Any PART NUMBER DESCRIPTION 2 Pin Berg Connector Banana Jack Pair Test Points SMT Inductor 6.8uH 30V N-channel MOSFET 10ohm 0ohm 5mohm 2Megohm 1Kohm 5-position Dipswitch Coiltronics International Rectifier A ny A ny Vishay Dale A ny A ny Any Transpower Technologies Semtech SO8 0603 0603 2512 0603 0603
PRELIMINARY
MANUFACTURER FORM FACTOR Berg
1
1
2003 Semtech Corp.
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SC1404
POWER MANAGEMENT Evaluation Board Gerber Plots
To p Inner2
Inner1
Bottom
2003 Semtech Corp.
25
www.semtech.com
SC1404
POWER MANAGEMENT Outline Drawing - SSOP-28 PRELIMINARY
2003 Semtech Corp.
26
www.semtech.com
SC1404
POWER MANAGEMENT Outline Drawing - TSSOP-28
Land Pattern - TSSOP-28
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
2003 Semtech Corp.
27
www.semtech.com

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